The present invention relates to a stack package, and more particularly to a stack package which reduces delay in transmission of an electrical signal and a method of manufacturing the same.
Semiconductor devices in most electronic products are found in a form of packages. Various shapes and sizes of semiconductor packages are required to cater to different characteristics of various electronic products.
The trend in the electronic industry requires that the semiconductor devices be capable of high capacity, high integration, and high speed operation. Any semiconductor package manufactured using a single semiconductor chip has limitations in accomplishing high integration and high capacity. For this reason, stack packages are drawing attention as they are capable of achieving higher memory density through stacking of multiple semiconductor chips.
In general, a stack package can be produced by either stacking several semiconductor chips in a unit package or stacking several unit packages each having a semiconductor chip. The stack package is designed such that each semiconductor chip in a unit package or each of the stacked unit packages receives the same external electrical signals.
The stack package can be formed at a chip-level or at a wafer-level.
A chip-level stack package is manufactured by stacking and molding the individual semiconductor chips that were separated into individual chips through sawing a wafer having undergone the semiconductor manufacturing processes. A wafer-level stack package is manufactured by stacking wafers having undergone the semiconductor manufacturing processes and packaging the stacked wafers together, and thereafter cutting the stacked wafers along the scribe lines to separate into chip-level pieces for manufacturing the packages in a final process step.
The wafer-level stack package is referred to as a chip-scale package, because the size of a package is about the same size as the semiconductor chip packaged therein. This reduces the package's footprint required for electrical connection and thereby increases the efficiency of the substrate hosting the package.
Also, the wafer-level stack packages require smaller mounting area and shorter wiring length than the conventional lead-type packages, and thus it is considered advantageous to apply the wafer-level stack packages in the high frequency devices.
However, the conventional stack packages require the wire rerouting processes or the wire bonding processes to electrically connect the upper and lower semiconductor chips or the stacked unit packages.
This leads to increased electrical connection lengths between the semiconductor chips or between the unit packages and prevents the stack packages from being easily applied to high-speed operation products.
Further, the increased length of the electrical connection in the conventional stack packages causes the sizes of the stack packages to also increase.